SPI Write Read N Frames
Write/Read the specified SPI channel. SPI is full duplex, therefore the write and read operations take place simultaneously.
<b>SPI Channel</b> specifies the device SPI channel to write/read to.
<b>Data</b> is a U8 array of data bytes to shift out starting with Data[0] to Data[n-1].
<b>SPI Frame Size</b> determinse the number of bytes shifted out between toggling CS.
<b>CS Channel</b> is the Chip Select (DIO) channel to use during the SPI transaction.
<b>CS Logic Level</b> specifies the logic level of the CS pin. Active low is most common and means that CS will idle high, then be driven low when a frame begins. The number of bytes specified in SPI Frame Size will be transfered, then CS will be driven high to end the frame. This process is repeated until all bytes in Data have been shifted out.
Inputs
CS Configuration
Specifies the chip select (slave select) configuration.
CS Channel specifies the digital output channel to use as chip select.
CS Logic Level specifies the polarity of the chip select output.
SPI Channel (0)
Specifies the SPI channel to write/read. If the LINX device has a single SPI master it is channel 0. If the LINX device has more than one SPI master the logical first SPI master is channel 0, the next is channel 1, etc.
LINX Resource
Contains LINX connection resources.
Data
The data to transmit. The first element in the array is the first to be transmitted.
SPI Frame Size (0)
Specifies the number of bytes to transmit between toggling chip select.
Error In
Describes error conditions that occur before this node runs. This input provides standard error in functionality.
Outputs
LINX Resource
Read Data
Error Out
